L'interface CPU

Reset et module:

module channel(
    input MCLK,
    input RESET,
    input [11:0] HPERIOD,
    input [11:0] DUTY,
    input [3:0] VOL,
    output reg [3:0] OUT
    );
    
    reg [11:0] CNT;
    
    assign OUT = OSC ? VOL : 12'd0;
    
    always @(posedge MCLK or posedge RESET)
    begin
        if (RESET)
        begin
            CNT <= 12'd0;
            OSC <= 1'b0;
        end
        else
        begin
			if (CNT)
			begin
                if (CNT == DUTY)
                    OSC <= 1'b1;		// Set sortie
                CNT <= CNT - 1'b1;	// Decrementer si > 0
            end
            else
            begin
                CNT <= HPERIOD;		// Reload
                OSC <= 1'b0;		// Reset sortie
            end
        end
    end
endmodule

reg [11:0] HPERIOD_A, HPERIOD_B, HPERIOD_C;
reg [11:0] DUTY_A, DUTY_B, DUTY_C;
reg [3:0] VOL_A, VOL_B, VOL_C;

wire [3:0] OUT_A, OUT_B, OUT_C;

channel CH_A(MCLK, RESET, HPERIOD_A, DUTY_A, VOL_A, OUT_A);
channel CH_B(MCLK, RESET, HPERIOD_B, DUTY_B, VOL_B, OUT_B);
channel CH_C(MCLK, RESET, HPERIOD_C, DUTY_C, VOL_C, OUT_C);